Area of research
Hardware and Architecture · Artificial Intelligence
Research interest
Research interests include Embedded Systems Design Techniques, Physical Unclonable Functions (PUFs) and Hardware Security, Security and Verification in Computing, and Parallel Computing and Optimization Techniques.
<scp>CGRA4ML</scp>
: A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing
PrioriFI: More Informed Fault Injection for Edge Neural Networks
Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT
Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT
<scp>Tailor</scp>
: Altering Skip Connections for Resource-Efficient Inference
TOP: Towards Open & Predictable Heterogeneous SoCs
FKeras: A Sensitivity Analysis Tool for Edge Neural Networks
eXpect: On the Security Implications of Violations in AXI Implementations
Pentimento: Data Remanence in Cloud FPGAs
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters
Junkyard Computing: Repurposing Discarded Smartphones to Minimize Carbon
Security Verification of the OpenTitan Hardware Root of Trust
A Framework for Design, Verification, and Management of SoC Access Control Systems
Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters
Adapting Skip Connections for Resource-Efficient FPGA Inference
Automated Generation, Verification, and Ranking of Secure SoC Access Control Policies
Sherlock: A Multi-Objective Design Space Exploration Framework
Cut and Forward: Safe and Secure Communication for FPGA System on Chips
Renée: New Life for Old Phones
A Remote Control System for Emergency Ventilators During SARS-CoV-2.
Underwater Depth Calibration Using a Commercial Depth Camera
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools
Hardware Information Flow Tracking
Hardware Information Flow Tracking
S2N2: A FPGA Accelerator for Streaming Spiking Neural Networks
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools
Low-cost 3D scanning systems for cultural heritage documentation
Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel
O(N)-Space Spatiotemporal Filter for Reducing Noise in Neuromorphic Vision Sensors
Distributed compressed sensing based channel estimation for underwater acoustic multiband transmissions
REU Site: Engineers for Exploration
Collaborative Research: SaTC: CORE: Medium: Pentimenti - Securing Cloud FPGAs from Analog Temporal Side Channels
Collaborative Research: SaTC: CORE: Medium: Hardware Security Insights: Analyzing Hardware Designs to Understand and Assess Security Weaknesses and Vulnerabilities
REU Site: Engineers for Exploration
REU Site: Engineers for Exploration
Student Travel Support for the International Symposium on Hardware-Oriented Security and Trust (HOST)
SaTC: STARSS: Small: Property Driven Hardware Security
TWC: Medium: Collaborative: Computational Blinking - Computer Architecture Techniques for Mitigating Side Channels
REU Site: Engineers for Exploration
TWC: Small: Employing Information Theoretic Metrics to Quantify and Enhance the Security of Hardware Designs
REU Site: Engineers for Exploration
I-Corps: Provable Hardware Design for Integrity and Security
SHF: Medium: Collaborative Research: Building Critical Systems with Verifiable Properties Using Gate Level Analysis
TC: Large: Collaborative Research: 3Dsec: Trustworthy System Security through 3-D Integrated Hardware
CSR-EHS:Architecture and Design Tools for Software Defined Acoustic Modem
CSR-EHS:Architecture and Design Tools for Software Defined Acoustic Modem
Adaptive Radiolocation for Mobile Sensor Networks