Area of research
Electrical and Electronic Engineering
Research interest
Research topics from publications: Advanced PWM Techniques for Multi-Level Inverters With a Multi-Level Active CM Noise Filter; A Multilevel Active CM Noise Power Filter for Multilevel Inverters; Improved De-Saturation Protection Circuits for Silicon Carbide MOSFET Gate Drivers; Dead-time Effect Compensation of a 5-Level ANPC WBG Inverter for High Power Density Aviation Applications; An Intelligent Gate Driver With Self-diagnosis and Prognosis for SiC MOSFETs; An Integrated Multi-level Active Gate Driver for SiC Power Modules; An Integrated Active Gate Driver for Half-bridge SiC MOSFET Power Modules; SiC-Based Intelligent Power Stage with Device Prognosis & Diagnosis and ZVRT Capability; Eliminating Dead-Time Effects with Zero-Current Clamping Control for WBG Multilevel Inverters; A Multi-level Active Power Filter for Common-Mode Voltage Attenuation in Multi-level Inverters. Representative work: Pulsewidth modulation (PWM)-based power electronics inverters are being widely used for various applications, including motor drives. However, the common-mode voltage (CMV) resulting from switching operations in the PWM inverters causes significant performance degradation of the system and can cause potential damage to motors. Since the effects of the CMV can be more severe in wide bandgap (WBG) and high switching frequency-based converter systems, various methods have been proposed to mitigate the CM noise issues. This work presents a multi-level inverter system composed of a multi-level inverter with a proposed multi-level active power filter (APF). For attenuating the CMV in multi-level i Common-mode voltage (CMV) caused by switching operations of power converters can significantly degrade the system's stability and performance. Since the effects of the CMV are more prominent in the wide-bandgap-based applications that require fast-switching slew rates, many research articles have been proposed to mitigate CM noise generated by the CMV. In addition, as topologies and control methods of the power converters become more complicated for better performance, more advanced CM noise attenuation methods are required accordingly. Therefore, this article proposes a CM noise attenuation method using a multilevel active CM noise power filter in a five-level inverter system. In this artic
A Multilevel Active CM Noise Power Filter for Multilevel Inverters
An Integrated Multi-level Active Gate Driver for SiC Power Modules
An Integrated Active Gate Driver for Half-bridge SiC MOSFET Power Modules
SiC-Based Intelligent Power Stage with Device Prognosis & Diagnosis and ZVRT Capability
Advanced PWM Techniques for Multi-Level Inverters With a Multi-Level Active CM Noise Filter
Improved De-Saturation Protection Circuits for Silicon Carbide MOSFET Gate Drivers
An Intelligent Gate Driver With Self-diagnosis and Prognosis for SiC MOSFETs
Eliminating Dead-Time Effects with Zero-Current Clamping Control for WBG Multilevel Inverters
A Multi-level Active Power Filter for Common-Mode Voltage Attenuation in Multi-level Inverters
An Integrated Active Gate Driver for SiC MOSFETs
Dead-time Effect Compensation of a 5-Level ANPC WBG Inverter for High Power Density Aviation Applications