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Chung‐Kuan Cheng

University of California San Diego · US
Area of research
Electrical and Electronic Engineering · Hardware and Architecture
Research interest
Research interests include VLSI and FPGA Design Techniques, Low-power high-performance VLSI design, Interconnection Networks and Systems, and VLSI and Analog Circuit Testing.
h-index
41
citations
7,254
works
422
NIH funding
—
primary concept
—
email
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Recent publications

Standard Cell Layout Generation: Review, Challenges, and Future Works
Proceedings of the 30th Asia and South Pacific Design Automation Conference 2025cited by 5position: contributordoi
Cell-Flex Metrics for Designing Optimal Standard Cell Layout with Enhanced Cell Layout Flexibility
Proceedings of the 2025 International Symposium on Physical Design 2025cited by 4position: contributordoi
An Updated Assessment of Reinforcement Learning for Macro Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025cited by 4position: contributordoi
Invited: Scaling Standard Cell Layout Using Track Height Compression and Design Technology Co-optimization
Proceedings of the 2025 International Symposium on Physical Design 2025cited by 2position: contributordoi
SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design 2024cited by 2position: contributordoi
Noise-Aware Circuit Clustering based on Analytical Placement Evolution
Proceedings of the 2024 ACM International Workshop on System-Level Interconnect Pathfinding 2024cited by 0position: contributordoi
Overview of 2024 CAD contest at ICCAD
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design 2024cited by 0position: contributordoi
Assessment of Reinforcement Learning for Macro Placement
2023cited by 34position: firstdoi
Assessment of Reinforcement Learning for Macro Placement
Proceedings of the 2023 International Symposium on Physical Design 2023cited by 32position: contributordoi
Assessing Pediatric Mild Traumatic Brain Injury and Its Recovery Using Resting-State Magnetoencephalography Source Magnitude Imaging and Machine Learning
Journal of Neurotrauma 2023cited by 14position: middledoi
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs
ACM Transactions on Design Automation of Electronic Systems 2023cited by 10position: contributordoi
Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration
Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding 2023cited by 6position: contributordoi
Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies
Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding 2023cited by 2position: contributordoi
Placement Initialization via Sequential Subspace Optimization with Sphere Constraints
Proceedings of the 2023 International Symposium on Physical Design 2023cited by 1position: contributordoi
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2022cited by 21position: contributordoi
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2022cited by 13position: contributordoi
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform
IEEE Access 2022cited by 8position: contributordoi
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation
IEEE Design & Test 2022cited by 1position: contributordoi
Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation
IEEE Embedded Systems Letters 2022cited by 0position: contributordoi
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2021cited by 50position: firstdoi
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2021cited by 49position: contributordoi
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2021cited by 45position: contributordoi
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs
2021cited by 25position: lastdoi
Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2021cited by 22position: firstdoi
Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2021cited by 20position: contributordoi
Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2021cited by 11position: contributordoi
SAT-Based On-Track Bus Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2021cited by 7position: contributordoi
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC
IEEE Embedded Systems Letters 2021cited by 5position: contributordoi
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2020cited by 42position: lastdoi
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2020cited by 14position: contributordoi

Grants

SHF: Small: Research on Standard Cell Layout to Facilitate the VLSI Technology Scaling
NSF2110419$547,8942021–2026PIRePORTER
SHF: Small: VLSI Circuit Simulation Using Parallel Processing
NSF1017864$482,0002010–2015PIRePORTER
Hybrid Clock Networks using Distortionless Transmission Lines
NSF0618163$75,0002006–2007PIRePORTER
Research on Interconnect-Dominated Floorplanning
NSF9987678$400,9012000–2004PIRePORTER
Research on Rapid Prototyping Systems Using Field Programmable Devices
NSF9529077$475,4791996–1999PIRePORTER
Research on Circuit Partitioning
NSF9315794$165,0001994–1997PIRePORTER
RIA: Research on Partitioning for High Speed and High Density Circuit Design
NSF9009260$68,0001990–1992PIRePORTER

Frequent collaborators

— · 26 papers (2019–2025)Bill Lin · University of Washington15 papers (2020–2025)Yucheng Wang · Shenzhen Polytechnic University9 papers (2023–2025)Daeyeal Lee · University of California San Diego8 papers (2020–2022)Andrew B. Kahng · UC San Diego Health System6 papers (2018–2023)— · 6 papers (2021–2022)— · 4 papers (2022–2023)Dongwon Park · University of California San Diego4 papers (2020–2022)— · 4 papers (2019–2021)Byeonggon Kang · Elsevier, Inc.4 papers (2023–2025)Mingxiong Huang · University of San Diego3 papers (2018–2023)Chia-Tung Ho · Nvidia (United States)3 papers (2020–2021)Bill Lin · University of Washington3 papers (2020–2021)Charles Huang · Stanford University3 papers (2018–2023)— · 3 papers (2014–2015)— · 3 papers (2014–2015)— · 3 papers (2014–2015)— · 3 papers (2020–2023)Uday Mallappa · Intel (United States)3 papers (2022–2023)— · 3 papers (2014–2015)