Area of research
Hardware and Architecture · Computer Networks and Communications
Research interest
Research interests include Computer science, Scalability, Router, Network on a chip, Cache, and Cache pollution.
SquareLoop: Explore Optimal Authentication Block Strategy for ML
TACOS: Topology-Aware Collective Algorithm Synthesizer for Distributed Machine Learning
Understanding Performance Implications of LLM Inference on CPUs
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering
Single-cycle collective communication over a shared network fabric
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
Breaking the on-chip latency barrier using SMART
SMART: A Single-Cycle Reconfigurable NoC for SoC Applications
SMART: a single-cycle reconfigurable NoC for SoC applications
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI