Area of research
Computer Networks and Communications · Hardware and Architecture
Research interest
Research interests include Parallel Computing and Optimization Techniques, Advanced Data Storage Technologies, Interconnection Networks and Systems, and Advanced Memory and Neural Computing.
<scp>FLEXPROF</scp>
: Flexible, Side-Channel-Free Memory Access
PATHFINDER: Practical Real-Time Learning for Data Prefetching
PATHFINDER: Practical Real-Time Learning for Data Prefetching
XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion
Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication
SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks
Wire-Aware Architecture and Dataflow for CNN Accelerators
Innovations in the Memory System
Secure DIMM: Moving ORAM Primitives Closer to Memory
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
Overcoming the challenges of crossbar resistive memory architectures
Efficiently prefetching complex address patterns
Improving memristor memory with sneak current sharing
Avoiding information leakage in the memory controller with fixed service policies
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
Near-Data Processing: Insights from a MICRO-46 Workshop
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers
MemZip: Exploring unconventional benefits from memory compression
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
Efficient scrub mechanisms for error-prone emerging memories
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access
SHF: Small: Acceleration Strategies for Emerging Life Science Workloads
SaTC: CORE: Small: Efficient Hardware-Aware and Hardware-Enabled Algorithms for Secure In-Memory Databases
CSR: Small: Adaptive Brink-of-Failure Memory Architectures for Future Technologies and Workloads
CSR: Medium: Energy-Efficient Architectures for Emerging Big-Data Workloads
Student Travel Support for the 2013 International Symposium on Computer Architecture (ISCA-40)
Student Travel Support for the 2011 International Symposium on Computer Architecture (ISCA-38)
Travel Support for the 2011 IEEE International Symposium on Performance Analysis of Systems and Software
SHF: Small: Hardware/Software Management of Large Multi-Core Memory Hierarchies
CPA-CSA: Algorithms and Implementations for Scalable Transactional Memory
CAREER: Exploring Heterogeneity Within Chip Multiprocessors
Exploiting Fast On-Chip Wires